This application claims the priority benefit of Taiwan application serial no. 89106031, filed Mar. 13, 2000.
1. Field of Invention
The present invention relates to fabrication method for a semiconductor device. Particularly, the invention relates to a method of fabricating an inter-metal dielectric (IMD) layer that is applicable to multilevel interconnects.
2. Description of Related Art
In an integrated circuit with two or more levels of interconnects, an inter-metal dielectric (IMD) layer must be placed between the levels for an isolation purpose. Generally, this dielectric layer needs to satisfy the following: its good film""s reliability and mechanical stability, low water absorption, and ease for integration, etc. A typical material for the IMD layer includes silicon oxide that has a dielectric constant of about 4. Alternatively, fluorinated silicate glass (FSG) is used to make the IMD layer, for the reason that FSG has a lower dielectric constant of about 3.5 as compared to undoped silicate glass (USG). With a lower dielectric constant, it is desirable for the IMD layer to reduce the RC time delay of the interconnect metallization. Thus, in terms of process simplicity and integrity, FSG is a better choice among other lower dielectric constant materials for making a low dielectric layer.
FIG. 1A and FIG. 1B are schematic, cross-sectional diagrams illustrating a conventional fabrication method for an IMD layer. Referring to FIG. 1A, a plurality of metal lines 102 are formed on a substrate 100. A gap-filled FSG layer 106 with turning on bias power and clamped the wafer by electrostatic chuck (ESC) is formed on the substrate 100 by high-density plasma chemical vapor deposition (HDPCVD), and it fills the gap between the metal lines 102. Prior to the gap-fill FSG layer, an USG 104 normally is introduced, preventing the metal line from being attacked by fluorine. Then, a cap layer 108 is formed on the gap-fill FSG layer 106, wherein the cap layer 108 is made of oxide by plasma enhanced chemical vapor deposition (PECVD). A chemical mechanical polishing (CMP) process is subsequently performed to planarize the cap layer 108, as shown in FIG. 1B.
On the substrate 100, the metal lines 102 are usually distributed in a conductive line region both with dense and loose areas, respectively. As a result, a large step height difference exists between the gap-fill FSG layer 106 on the dense conductive line region 102a and that on the loose conductive line region 102b, after the biased-clamped FSG layer 106 and the cap layer 108 being formed. Thus, it is difficult to control a polishing stop for chemical mechanical polishing (CMP), and over-polishing easily arises. As a result, the gap-fill FSG layer 106 may be exposed, probably resulting in the instability of fluorine. Intrinsically, the gap-fill FSG layer exhibits a chemically or physically hydrophilic behavior. Therefore, the gap-fill FSG layer 106 easily absorbs moisture when the gap-fill FSG layer 106 is in contact with CMP slurry. The absorbed moisture and/or solvent certainly increases the dielectric constant of the IMD layer and can cause further problems when the IMD layer is exposed to a thermal process, such as an anneal process. After high temperature anneal processes, the moisture would be absorbed to result in a severe blister if the out gas is sealed in subsequent deposition processes.
Furthermore, fluorine is known as a reactive chemical species, as it can produce a rigorous chemical reaction to produce HF that is a more reactive intermediate. HF can result in metal corrosion, oxide degradation, peeling at the metal/IMD layer interface in subsequent processes when a metal plug is formed. Therefore, the FSG layers with high fluorine content can lead to an instability of processes, which degrades device reliability.
The invention provides a fabrication method for an inter-metal dielectric layer applicable to multi-level interconnects. A first liner layer is formed, followed by depositing a dielectric layer on the first liner layer. A second liner layer is then formed on the dielectric layer, while a cap layer is formed on the second liner layer. A planarization process is performed on the cap layer until the second liner layer is exposed.
As embodied and broadly described herein, the invention provides a fabrication method for an IMD layer applicable to a semiconductor process. A substrate is provided with a metal layer formed thereon. A gap-fill fluorinated silicon glass (FSG) layer is formed on the substrate and covers the metal layer. A FSG layer with low fluorine content is then formed on the gap-fill FSG layer, follows by forming a planarized oxide layer on the oxide cap layer. The method prevents a direct contact between the CMP slurry and the gap-fill FSG layer, to result in metal corrosion, peeling, as well as an increase of dielectric constant.
According to the present invention, an additional FSG layer with low fluorine content can be formed on the substrate prior to forming the gap-fill FSG layer. The FSG layer with low fluorine content can serve as a liner to provide a better adhesion between the gap-fill FSG layer and the metal layer, to prevent a metal corrosion, and to provide a lower dielectric constant than that of a conventional undoped silicon glass (USG) layer. Since the gap-fill FSG layer with higher fluorine content is protected by two FSG layers with low fluorine content, the surface of the gap-filled FSG layer is not exposed. As a result, this prevents the metal corrosion, degradation of the oxide, peeling issue at a metal/IMD interface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.